Advances in device integration technology have led to the development of a three-dimensional stacked LSI approach, in contrast to the conventional two-dimensional LSI approach. Some types of three dimensional integration include package stacking, die stacking, and wafer stacking. Among wafer stacking approaches, a technique called Through-Silicon-Via (TSV) can be used to extend a via hole through a substrate so that a conductive electrode or via may be formed that completely penetrates the substrate, creating vertical connections through the body of a chip. In turn, multiple substrates including TSVs can be stacked on one another to achieve three dimensional integration. In particular, the TSVs of different substrates can conduct signals from one substrate to another without the need to use, for example, wires.
Two approaches that can be used in the formation of TSVs include a “via first” approach and a “via last” approach. According to a via first approach, TSVs are formed through the substrate before back end processing, such that vias can be formed in the substrates to only partially penetrate the entire substrate. According to the via last approach, the vias can be formed after the back end processing and/or after a bonding process. Subsequently, the substrates can be thinned and bound together to achieve a three-dimensional stacked structure.
TSV structures are also discussed in, for example, in the following documents: U.S. Patent Application Publication No. 2008/0036082; U.S. Patent Application Publication No. 2008/0211081; and Japanese Patent No. 3896038.